1. Field of the Invention
This invention relates to a method of fabricating a semiconductor device, and in more particular to a method of fabricating a semiconductor device using plasma etching as dry etching.
2. Description of the Prior Art
When a deep trench 9 is formed in a single-crystal silicon substrate 1 using a photoresist as a mask material 2, as shown in FIGS. 1A to 1B, and if etching is performed using an etching gas containing SF.sub.6 as the main etching gas, for example, SF.sub.6 +F.sub.115, SF.sub.6 +F.sub.12, SF.sub.6 +CCl.sub.4, SF.sub.6 +Cl.sub.2, or SF.sub.6 +F.sub.21, due to deposition of carbon from the photoresist, projecting parts 10 are formed at an opening portion 11 of the trench 9 so that the opening portion 11 becomes narrow (see FIG. 1B).
When an insulating material 4 such as polysilicon or an oxide film is filled or buried into the aforementioned trench 9, it is easy for a cavity, i.e. a nest 8 to be formed in the opening portion 11 of the trench 9 where it is not completely filled with the insulating material (see FIG. 1C).
When this kind of cavity occurs, a depression is formed when etching is performed, and when heat treatment is performed, it becomes easy for stress to occur in the silicon substrate 1.
Also, as shown in FIG. 2A, when forming wiring 13 by etching a polysilicon film 5 (resistance wire, etc.) on a single-crystal silicon substrate 1 using a photoresist as a mask 2 and using an etching as which contains SF.sub.6 as the main etching gas, if the etching anisotropy is increased, coverage of an interlayer insulating film or insulator 6 and its top wiring material layer 7 on the wiring 13 formed in a later process becomes poor (see FIG. 2C). When etching is performed isotropically in an attempt to improve the coverage, and when P or As is used as a dopant in the polysilicon film 5, sideways etching or undercutting 12 becomes large, and thus it is difficult to control the dimensions of the wiring 13 (see FIG. 2B).
In the prior etching method:
(1) When a deep trench is formed in the silicon substrate by etching and an insulating material is filled or buried into the trench, it is easy for a cavity or cavities to be formed in or near the opening portion causing the trench to be poorly filled and causing stress in the single-crystal silicon substrate.
(2) When wiring is formed by etching the polysilicon, a problem exists in that coverage of the top layers on the wiring is poor and the dimension of the wiring are poor due to sideways etching of the polysilicon itself.